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Dynamic random-access memory

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Computer memory types
Volatile
RAM
  • DRAM
  • SRAM
Historical
  • Williams–Kilburn tube (1946)
  • Delay line memory (1947)
  • Mellon optical memory (1951)
  • Selectron tube (1952)
  • Dekatron
  • Z-RAM (2002)
  • T-RAM (2009)
Non-volatile
ROM
  • Mask ROM
  • PROM
  • EPROM
  • EEPROM
  • Flash memory
NVRAM
  • ReRAM
Early stage NVRAM
  • FeRAM
  • MRAM
  • PCM (3D XPoint)
  • FeFET memory
Magnetic
Optical
  • Optical disc
  • 5D optical data storage
In development
  • CBRAM
  • Racetrack memory
  • NRAM
  • Millipede memory
  • FJG RAM
Historical
  • Paper data storage (1725)
  • Drum memory (1932)
  • Magnetic-core memory (1949)
  • Floppy disk (1950)
  • Plated wire memory (1957)
  • Core rope memory (1960s)
  • Thin-film memory (1962)
  • Disk pack (1962)
  • Twistor memory (~1968)
  • Bubble memory (~1970)
Related

Dynamic random-access memory (DRAM) is a type of random-access memory (RAM) that that stores each bit of data in a memory cell consisting of a tiny capacitor and a transistor, both typically based on metal–oxide–semiconductor (MOS) technology. DRAM typically takes the form of an integrated circuit chip, which can consist of dozens to billions of memory cells.

The capacitor can be either charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. Since even "non-conducting" transistors always leak a small amount, the capacitors will slowly discharge, and the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to static random-access memory (SRAM) and other static types of memory. Unlike flash memory, DRAM is volatile memory (vs. non-volatile memory), since it loses its data quickly when power is removed. However, DRAM does exhibit limited data remanence.

DRAM is widely used in digital electronics where low-cost and high-capacity memory is required. One of the largest applications for DRAM is the main memory (colloquially called the "RAM") in modern computers; and as the main memories of components used in these computers such as graphics cards (where the "main memory" is called the graphics memory). In contrast, SRAM, which is faster and more expensive than DRAM, is typically used where speed is of greater concern than cost, such as the cache memories in processors.

The advantage of DRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared to four or six transistors in SRAM. This allows DRAM to reach very high densities. The transistors and capacitors used are extremely small; billions can fit on a single memory chip. Due to the dynamic nature of its memory cells, DRAM consumes relatively large amounts of power, with different ways for managing the power consumption.[1]

As of 2018, a "key characteristic of the DRAM market is that there are currently only three major suppliers — Micron Technology, SK Hynix and Samsung Electronics" that are "keeping a pretty tight rein on their capacity".[2] There is also Kioxia (previously Toshiba Memory Corporation after 2017 spin-off). Other manufacturers make and sell DIMMs (but not the DRAM chips in them), such as Kingston Technology, and some manufacturers that sell stacked DRAM (used e.g. in the fastest supercomputers on the exascale). Others sell DRAMintegrated into other products, such as Fujitsu inits CPUs, AMD in GPUs, and Nvidia with HBM2 in some of their GPU chips.

History[]

The cryptanalytic machine code-named "Aquarius" used at Bletchley Park during World War II incorporated a hard-wired dynamic memory. Paper tape was read and the characters on it "were remembered in a dynamic store. ... The store used a large bank of capacitors, which were either charged or not, a charged capacitor representing cross (1) and an uncharged capacitor dot (0). Since the charge gradually leaked away, a periodic pulse was applied to top up those still charged (hence the term 'dynamic')".[3]

Bipolar DRAM[]

The earliest forms of DRAM mentioned above used bipolar transistors.[4] The Toshiba Toscal BC-1411 electronic calculator, which was introduced in either 1965,[5][6][7] used a form of DRAM built from discrete components.[6] It used a form of capacitive bipolar DRAM, storing 180-bit data on discrete memory cells, consisting of germanium bipolar transistors and capacitors.[8][9]

While bipolar DRAM offered improved performance over magnetic-core memory, bipolar DRAM could not compete with the lower price of the then-dominant magnetic-core memory.[4]

MOS DRAM[]

See also: MOS memory
Original 1T1C DRAM design

A schematic drawing depicting the cross-section of the original one-transistor, one-capacitor NMOS DRAM cell. It was patented in 1968.

The invention of the metal–oxide–semiconductor field-effect transistor (MOS transistor) by Mohamed M. Atalla and Dawon Kahng at Bell Labs in 1959,[10] led to the development of metal–oxide–semiconductor (MOS) memory at Fairchild Semiconductor in 1964,[11][12] in the form of static random-access memory (SRAM).[11] In addition to higher speeds, MOS semiconductor memory was cheaper and consumed less power than magnetic core memory.[11] SRAM became an alternative to magnetic-core memory, but required six MOS transistors for each bit of data.[13] Commercial use of SRAM began in 1965, when IBM introduced the SP95 memory chip for the System/360 Model 95.[14]

DRAM allowed replacement of a 4 or 6-transistor latch circuit by a single transistor for each memory bit, greatly increasing memory density at the cost of volatility. Data was stored in the tiny capacitance of each transistor, and had to be periodically refreshed every few milliseconds before the charge could leak away.

MOS technology is the basis for modern DRAM. In 1966, Dr. Robert H. Dennard at the IBM Thomas J. Watson Research Center was working on MOS memory. While examining the characteristics of MOS technology, he found it was capable of building capacitors, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This led to his development of a single-transistor DRAM memory cell.[13] In 1967, Dennard filed a patent under IBM for a single-transistor DRAM memory cell, based on MOS technology.[15]

The invention of the MOSFET (metal-oxide-semiconductor field-effect transistor), also known as the MOS transistor, by Mohamed Atalla and Dawon Kahng at Bell Labs in 1959,[16] led to the development of metal-oxide-semiconductor (MOS) DRAM.[17] In 1966, Dr. Robert Dennard at the IBM Thomas J. Watson Research Center was working on MOS memory and was trying to create an alternative to SRAM which required six MOS transistors for each bit of data. While examining the characteristics of MOS technology, he found it was capable of building capacitors, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This led to his development of the single-transistor MOS DRAM memory cell.[17] He filed a patent in 1967, and was granted U.S. patent number 3,387,286 in 1968.[18] The development of silicon-gate MOS integrated circuit (MOS IC) at Fairchild in 1968 enabled the production of MOS memory chips.[19]

MOS DRAM chips were commercialized in 1969 by Advanced Memory system, Inc of Sunnyvale, CA. This 1000 bit chip was sold to Honeywell, Raytheon, Wang Laboratories, and others. The same year, Honeywell asked Intel to make a DRAM using a three-transistor cell that they had developed. This became the Intel 1102 in early 1970.[20] However, the 1102 had many problems, prompting Intel to begin work on their own improved design, in secrecy to avoid conflict with Honeywell. This became the first commercially available DRAM, the Intel 1103, in October 1970, despite initial problems with low yield until the fifth revision of the masks. The 1103 was designed by Joel Karp and laid out by Pat Earhart. The masks were cut by Barbara Maness and Judy Garcia.[21] The first commercial DRAM IC chip was the Intel 1103, which was manufactured on an 8 μm MOS process with a capacity of 1 kbit, and was released in 1970.[11][22][23] MOS memory overtook magnetic-core memory as the dominant memory technology in the early 1970s.[11]

As density increased to 64 kbit in the early 1980s, US manufacturers were overtaken by Japanese DRAM manufacturers, which dominated the US and worldwide markets during the 1980s and 1990s.

In 1985, when 64K DRAM memory chips were the most common memory chips used in computers, and when more than 60 percent of those chips were produced by Japanese companies, semiconductor makers in the United States accused Japanese companies of export dumping for the purpose of driving makers in the United States out of the commodity memory chip business.[24] Early in 1985, Gordon Moore decided to withdraw Intel from producing DRAM.[25] By 1986, all United States chip makers had stopped making DRAMs.[26]

SDRAM[]

Main article: Synchronous dynamic random-access memory

Synchronous dynamic random-access memory (SDRAM) was developed by Samsung Electronics in South Korea. The first commercial SDRAM chip was the Samsung KM48SL2000, which had a capacity of 16 Mbit.[27] It was introduced by Samsung in 1992,[28] and mass-produced in 1993.[27] The first commercial DDR SDRAM (double data rate SDRAM) memory chip was Samsung's 64 Mbit DDR SDRAM chip, released in June 1998.[29] GDDR (graphics DDR) is a form of DDR SGRAM (synchronous graphics RAM), which was first released by Samsung as a 16 Mbit memory chip in 1998.[30]

In 2001, Japanese DRAM makers accused Korean DRAM manufacturers of dumping.[31] In 2002, US computer makers made claims of DRAM price fixing.

Versions[]

While the fundamental DRAM cell and array has maintained the same basic structure (and performance) for many years, there have been many different interfaces for communicating with DRAM chips. When one speaks about "DRAM types", one is generally referring to the interface that is used.

DRAM can be divided into asynchronous and synchronous DRAM. In addition, graphics DRAM is specially designed for graphics tasks, and can be asynchronous or synchronous DRAM in nature. Pseudostatic RAM (PSRAM) have an architecture and interface that closely mimics the operation and interface of static RAM. Lastly, 1T DRAM uses a capacitorless design, as opposed to the usual 1T/1C (one transistor/one capacitor) designs of conventional DRAM.

Asynchronous DRAM[]

Principles of operation[]

An asynchronous DRAM chip has power connections, some number of address inputs (typically 12), and a few (typically one or four) bidirectional data lines. There are four active-low control signals:

  • RAS, the Row Address Strobe. The address inputs are captured on the falling edge of RAS, and select a row to open. The row is held open as long as RAS is low.
  • CAS, the Column Address Strobe. The address inputs are captured on the falling edge of CAS, and select a column from the currently open row to read or write.
  • WE, Write Enable. This signal determines whether a given falling edge of CAS is a read (if high) or write (if low). If low, the data inputs are also captured on the falling edge of CAS.
  • OE, Output Enable. This is an additional signal that controls output to the data I/O pins. The data pins are driven by the DRAM chip if RAS and CAS are low, WE is high, and OE is low. In many applications, OE can be permanently connected low (output always enabled), but it can be useful when connecting multiple memory chips in parallel.

This interface provides direct control of internal timing. When RAS is driven low, a CAS cycle must not be attempted until the sense amplifiers have sensed the memory state, and RAS must not be returned high until the storage cells have been refreshed. When RAS is driven high, it must be held high long enough for precharging to complete.

Although the DRAM is asynchronous, the signals are typically generated by a clocked memory controller, which limits their timing to multiples of the controller's clock cycle.

RAS Only Refresh (ROR)[]

Classic asynchronous DRAM is refreshed by opening each row in turn.

The refresh cycles are distributed across the entire refresh interval in such a way that all rows are refreshed within the required interval. To refresh one row of the memory array using RAS Only Refresh, the following steps must occur:

  1. The row address of the row to be refreshed must be applied at the address input pins.
  2. RAS must switch from high to low. CAS must remain high.
  3. At the end of the required amount of time, RAS must return high.

This can be done by supplying a row address and pulsing RAS low; it is not necessary to perform any CAS cycles. An external counter is needed to iterate over the row addresses in turn.[32]

CAS before RAS refresh (CBR)[]

For convenience, the counter was quickly incorporated into the DRAM chips themselves. If the CAS line is driven low before RAS (normally an illegal operation), then the DRAM ignores the address inputs and uses an internal counter to select the row to open. This is known as CAS-before-RAS (CBR) refresh. This became the standard form of refresh for asynchronous DRAM, and is the only form generally used with SDRAM.

Hidden refresh[]

Given support of CAS-before-RAS refresh, it is possible to deassert RAS while holding CAS low to maintain data output. If RAS is then asserted again, this performs a CBR refresh cycle while the DRAM outputs remain valid. Because data output is not interrupted, this is known as hidden refresh.[33]

Page mode DRAM[]

Page mode DRAM is a minor modification to the first-generation DRAM IC interface which improved the performance of reads and writes to a row by avoiding the inefficiency of precharging and opening the same row repeatedly to access a different column. In Page mode DRAM, after a row was opened by holding RAS low, the row could be kept open, and multiple reads or writes could be performed to any of the columns in the row. Each column access was initiated by asserting CAS and presenting a column address. For reads, after a delay (tCAC), valid data would appear on the data out pins, which were held at high-Z before the appearance of valid data. For writes, the write enable signal and write data would be presented along with the column address.[34]

Page mode DRAM was later improved with a small modification which further reduced latency. DRAMs with this improvement were called fast page mode DRAMs (FPM DRAMs). In page mode DRAM, CAS was asserted before the column address was supplied. In FPM DRAM, the column address could be supplied while CAS was still deasserted. The column address propagated through the column address data path, but did not output data on the data pins until CAS was asserted. Prior to CAS being asserted, the data out pins were held at high-Z. FPM DRAM reduced tCAC latency.[35]

Static column is a variant of fast page mode in which the column address does not need to be stored in, but rather, the address inputs may be changed with CAS held low, and the data output will be updated accordingly a few nanoseconds later.[35]

Nibble mode is another variant in which four sequential locations within the row can be accessed with four consecutive pulses of CAS. The difference from normal page mode is that the address inputs are not used for the second through fourth CAS edges; they are generated internally starting with the address supplied for the first CAS edge.[35]

Extended data out DRAM (EDO DRAM)[]
Pair32mbEDO-DRAMdimms

A pair of 32 MB EDO DRAM modules.

EDO DRAM, sometimes referred to as Hyper Page Mode enabled DRAM, is similar to Fast Page Mode DRAM with the additional feature that a new access cycle can be started while keeping the data output of the previous cycle active. This allows a certain amount of overlap in operation (pipelining), allowing somewhat improved performance. It was 5% faster than FPM DRAM, which it began to replace in 1995, when Intel introduced the 430FX chipset that supported EDO DRAM.

To be precise, EDO DRAM begins data output on the falling edge of CAS, but does not stop the output when CAS rises again. It holds the output valid (thus extending the data output time) until either RAS is deasserted, or a new CAS falling edge selects a different column address.

Single-cycle EDO has the ability to carry out a complete memory transaction in one clock cycle. Otherwise, each sequential RAM access within the same page takes two clock cycles instead of three, once the page has been selected. EDO's performance and capabilities allowed it to somewhat replace the then-slow L2 caches of PCs. It created an opportunity to reduce the immense performance loss associated with a lack of L2 cache, while making systems cheaper to build. This was also good for notebooks due to difficulties with their limited form factor, and battery life limitations. An EDO system with L2 cache was tangibly faster than the older FPM/L2 combination.

Single-cycle EDO DRAM became very popular on video cards towards the end of the 1990s. It was very low cost, yet nearly as efficient for performance as the far more costly VRAM.

Burst EDO DRAM (BEDO DRAM)[]

An evolution of EDO DRAM, Burst EDO DRAM, could process four memory addresses in one burst, for a maximum of 5‐1‐1‐1, saving an additional three clocks over optimally designed EDO memory. It was done by adding an address counter on the chip to keep track of the next address. BEDO also added a pipeline stage allowing page-access cycle to be divided into two parts. During a memory-read operation, the first part accessed the data from the memory array to the output stage (second latch). The second part drove the data bus from this latch at the appropriate logic level. Since the data is already in the output buffer, quicker access time is achieved (up to 50% for large blocks of data) than with traditional EDO.

Although BEDO DRAM showed additional optimization over EDO, by the time it was available the market had made a significant investment towards synchronous DRAM, or SDRAM [2]. Even though BEDO RAM was superior to SDRAM in some ways, the latter technology quickly displaced BEDO.

Synchronous dynamic RAM (SDRAM)[]

Main article: Synchronous dynamic random-access memory

SDRAM significantly revises the asynchronous memory interface, adding a clock (and a clock enable) line. All other signals are received on the rising edge of the clock.

The /RAS and /CAS inputs no longer act as strobes, but are instead, along with /WE, part of a 3-bit command:

SDRAM Command summary
/CS /RAS /CAS /WE Address Command
H x x x x Command inhibit (No operation)
L H H H x No operation
L H H L x Burst Terminate: stop a read or write burst in progress
L H L H column Read from currently active row
L H L L column Write to currently active row
L L H H row Activate a row for read and write
L L H L x Precharge (deactivate) the current row
L L L H x Auto refresh: Refresh one row of each bank, using an internal counter
L L L L mode Load mode register: Address bus specifies DRAM operation mode.

The /OE line's function is extended to a per-byte "DQM" signal, which controls data input (writes) in addition to data output (reads). This allows DRAM chips to be wider than 8 bits while still supporting byte-granularity writes.

Many timing parameters remain under the control of the DRAM controller. For example, a minimum time must elapse between a row being activated and a read or write command. One important parameter must be programmed into the SDRAM chip itself, namely the CAS latency. This is the number of clock cycles allowed for internal operations between a read command and the first data word appearing on the data bus. The "Load mode register" command is used to transfer this value to the SDRAM chip. Other configurable parameters include the length of read and write bursts, i.e. the number of words transferred per read or write command.

The most significant change, and the primary reason that SDRAM has supplanted asynchronous RAM, is the support for multiple internal banks inside the DRAM chip. Using a few bits of "bank address" which accompany each command, a second bank can be activated and begin reading data while a read from the first bank is in progress. By alternating banks, an SDRAM device can keep the data bus continuously busy, in a way that asynchronous DRAM cannot.

Single data rate synchronous DRAM (SDR SDRAM)[]

See also: SDR SDRAM

Single data rate SDRAM (sometimes known as SDR) is a synchronous form of DRAM.

Double data rate synchronous DRAM (DDR SDRAM)[]

Main articles: DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, and DDR4 SDRAM

Double data rate SDRAM (DDR) was a later development of SDRAM, used in PC memory beginning in 2000. Subsequent versions are numbered sequentially (DDR2, DDR3, etc.). DDR SDRAM internally performs double-width accesses at the clock rate, and uses a double data rate interface to transfer one half on each clock edge. DDR2 and DDR3 increased this factor to 4× and 8×, respectively, delivering 4-word and 8-word bursts over 2 and 4 clock cycles, respectively. The internal access rate is mostly unchanged (200 million per second for DDR-400, DDR2-800 and DDR3-1600 memory), but each access transfers more data.

Direct Rambus DRAM (DRDRAM)[]

Main article: RDRAM

Direct RAMBUS DRAM (DRDRAM) was developed by Rambus.

Reduced Latency DRAM (RLDRAM)[]

Main article: RLDRAM

Reduced Latency DRAM is a high performance double data rate (DDR) SDRAM that combines fast, random access with high bandwidth, mainly intended for networking and caching applications.

Graphics RAM[]

These are asynchronous and synchronous DRAMs designed for graphics-related tasks such as texture memory and framebuffers, and can be found on video cards.

Video DRAM (VRAM)[]

Main article: VRAM

VRAM is a dual-ported variant of DRAM that was once commonly used to store the frame-buffer in some graphics adaptors.

Window DRAM (WRAM)[]

WRAM is a variant of VRAM that was once used in graphics adaptors such as the Matrox Millennium and ATI 3D Rage Pro. WRAM was designed to perform better and cost less than VRAM. WRAM offered up to 25% greater bandwidth than VRAM and accelerated commonly used graphical operations such as text drawing and block fills.[36]

Multibank DRAM (MDRAM)[]

Multibank DRAM is a type of specialized DRAM developed by MoSys. It is constructed from small memory banks of 256 KB, which are operated in an interleaved fashion, providing bandwidths suitable for graphics cards at a lower cost to memories such as SRAM. MDRAM also allows operations to two banks in a single clock cycle, permitting multiple concurrent accesses to occur if the accesses were independent. MDRAM was primarily used in graphic cards, such as those featuring the Tseng Labs ET6x00 chipsets. Boards based upon this chipset often had the unusual capacity of 2.25 MB because of MDRAM's ability to be implemented more easily with such capacities. A graphics card with 2.25 MB of MDRAM had enough memory to provide 24-bit color at a resolution of 1024×768—a very popular setting at the time.

Synchronous graphics RAM (SGRAM)[]

SGRAM is a specialized form of SDRAM for graphics adaptors. It adds functions such as bit masking (writing to a specified bit plane without affecting the others) and block write (filling a block of memory with a single colour). Unlike VRAM and WRAM, SGRAM is single-ported. However, it can open two memory pages at once, which simulates the dual-port nature of other video RAM technologies.

Graphics double data rate SDRAM (GDDR SDRAM)[]

Main article: GDDR

Graphics double data rate SDRAM (GDDR SDRAM) is a type of specialized DDR SDRAM designed to be used as the main memory of graphics processing units (GPUs). GDDR SDRAM is distinct from commodity types of DDR SDRAM such as DDR3, although they share some core technologies. Their primary characteristics are higher clock frequencies for both the DRAM core and I/O interface, which provides greater memory bandwidth for GPUs. As of 2016, there are five successive generations of GDDR: GDDR2, GDDR3, GDDR4, GDDR5, and GDDR5X.

Pseudostatic RAM (PSRAM)[]

Olivetti JP90 - Toshiba TC518129CFWL-80 on controller-8514

1 Mbit high speed CMOS pseudo static RAM, made by Toshiba

PSRAM or PSDRAM is dynamic RAM with built-in refresh and address-control circuitry to make it behave similarly to static RAM (SRAM). It combines the high density of DRAM with the ease of use of true SRAM. PSRAM (made by Numonyx) is used in the Apple iPhone and other embedded systems such as XFlar Platform.[37]

Some DRAM components have a "self-refresh mode". While this involves much of the same logic that is needed for pseudo-static operation, this mode is often equivalent to a standby mode. It is provided primarily to allow a system to suspend operation of its DRAM controller to save power without losing data stored in DRAM, rather not to allow operation without a separate DRAM controller as is the case with PSRAM.

An embedded variant of PSRAM is sold by MoSys under the name 1T-SRAM. It is technically DRAM, but behaves much like SRAM. It is used in Nintendo GameCube and Wii video game consoles.

Timeline[]

See also: Flash memory#Timeline, Read-only memory#Timeline, and Transistor count#Memory

DRAM[]

Dynamic random-access memory (DRAM)
Date of introduction Chip name Capacity (bits) DRAM type Manufacturer(s) Process MOSFET Area Ref
1965 — 1 bit DRAM (cell) Toshiba — — — [38][6]
1967 — 1 bit DRAM (cell) IBM — MOS — [15][39]
1968 ? 256 bit DRAM (IC) Fairchild ? PMOS ? [11]
1969 — 1 bit DRAM (cell) Intel — PMOS — [39]
1970 1102 1 kbit DRAM (IC) Intel, Honeywell ? PMOS ? [39]
1103 1 kbit DRAM Intel 8,000 nm PMOS 10 mm2 [40][41][22]
1971 μPD403 1 kbit DRAM NEC ? NMOS ? [42]
? 2 kbit DRAM General Instrument ? PMOS 13 mm2 [43]
1972 2107 4 kbit DRAM Intel ? NMOS ? [44][45]
1973 ? 8 kbit DRAM IBM ? PMOS 19 mm2 [43]
1975 2116 16 kbit DRAM Intel ? NMOS ? [46][11]
1977 ? 64 kbit DRAM NTT ? NMOS 35 mm2 [43]
1979 MK4816 16 kbit PSRAM Mostek ? NMOS ? [47]
? 64 kbit DRAM Siemens ? VMOS 25 mm2 [43]
1980 ? 256 kbit DRAM NEC, NTT 1,000–1,500 nm NMOS 34–42 mm2 [43]
1981 ? 288 kbit DRAM IBM ? MOS 25 mm2 [48]
1983 ? 64 kbit DRAM Intel 1,500 nm CMOS 20 mm2 [43]
256 kbit DRAM NTT ? CMOS 31 mm2
January 5, 1984 ? 8 Mbit DRAM Hitachi ? MOS ? [49][50]
February 1984 ? 1 Mbit DRAM Hitachi, NEC 1,000 nm NMOS 74–76 mm2 [43][51]
NTT 800 nm CMOS 53 mm2 [43][51]
1984 TMS4161 64 kbit DPRAM (VRAM) Texas Instruments ? NMOS ? [52][53]
January 1985 μPD41264 256 kbit DPRAM (VRAM) NEC ? NMOS ? [54][55]
June 1986 ? 1 Mbit PSRAM Toshiba ? CMOS ? [56]
1986 ? 4 Mbit DRAM NEC 800 nm NMOS 99 mm2 [43]
Texas Instruments, Toshiba 1,000 nm CMOS 100–137 mm2
1987 ? 16 Mbit DRAM NTT 700 nm CMOS 148 mm2 [43]
October 1988 ? 512 kbit HSDRAM IBM 1,000 nm CMOS 78 mm2 [57]
1991 ? 64 Mbit DRAM Matsushita, Mitsubishi, Fujitsu, Toshiba 400 nm CMOS ? [58]
1993 ? 256 Mbit DRAM Hitachi, NEC 250 nm CMOS ?
1995 ? 4 Mbit DPRAM (VRAM) Hitachi ? CMOS ? [59]
January 9, 1995 ? 1 Gbit DRAM NEC 250 nm CMOS ? [60][59]
Hitachi 160 nm CMOS ?
1996 ? 4 Mbit FRAM Samsung ? NMOS ? [61]
1997 ? 4 Gbit QLC NEC 150 nm CMOS ? [58]
1998 ? 4 Gbit DRAM Hyundai ? CMOS ? [62]
June 2001 TC51W3216XB 32 Mbit PSRAM Toshiba ? CMOS ? [63]
February 2001 ? 4 Gbit DRAM Samsung 100 nm CMOS ? [58][64]

SDRAM[]

This section is transcluded from Synchronous dynamic random-access memory. (edit | history)
Synchronous dynamic random-access memory (SDRAM)
Date of introduction Chip name Capacity (bits) SDRAM type Manufacturer(s) Process MOSFET Area Ref
1992 KM48SL2000 16 Mb SDR Samsung ? CMOS ? [65][27]
1996 MSM5718C50 18 Mb RDRAM Oki ? CMOS 325 mm² [66]
N64 RDRAM 36 Mb RDRAM NEC ? CMOS ? [67]
? 1 Gb SDR Mitsubishi 150 nm CMOS ? [58]
1997 ? 1 Gb SDR Hyundai ? SOI ? [62]
1998 MD5764802 64 Mb RDRAM Oki ? CMOS 325 mm² [66]
March 1998 Direct RDRAM 72 Mb RDRAM Rambus ? CMOS ? [68]
June 1998 ? 64 Mb DDR Samsung ? CMOS ? [69][70][71]
1998 ? 64 Mb DDR Hyundai ? CMOS ? [62]
128 Mb SDR Samsung ? CMOS ? [72][70]
1999 ? 128 Mb DDR Samsung ? CMOS ? [70]
1 Gb DDR Samsung 140 nm CMOS ? [58]
2000 GS eDRAM 32 Mb eDRAM Sony, Toshiba 180 nm CMOS 279 mm² [73]
2001 ? 288 Mb RDRAM Hynix ? CMOS ? [74]
? DDR2 Samsung 100 nm CMOS ? [71][58]
2002 ? 256 Mb SDR Hynix ? CMOS ? [74]
2003 EE+GS eDRAM 32 Mb eDRAM Sony, Toshiba 90 nm CMOS 86 mm² [73]
? 72 Mb DDR3 Samsung 90 nm CMOS ? [75]
512 Mb DDR2 Hynix ? CMOS ? [74]
Elpida 110 nm CMOS ? [76]
1 Gb DDR2 Hynix ? CMOS ? [74]
2004 ? 2 Gb DDR2 Samsung 80 nm CMOS ? [77]
2005 EE+GS eDRAM 32 Mb eDRAM Sony, Toshiba 65 nm CMOS 86 mm² [78]
Xenos eDRAM 80 Mb eDRAM NEC 90 nm CMOS ? [79]
? 512 Mb DDR3 Samsung 80 nm CMOS ? [71][80]
2006 ? 1 Gb DDR2 Hynix 60 nm CMOS ? [74]
2008 ? ? LPDDR2 Hynix ?
April 2008 ? 8 Gb DDR3 Samsung 50 nm CMOS ? [81]
2008 ? 16 Gb DDR3 Samsung 50 nm CMOS ?
2009 ? ? DDR3 Hynix 44 nm CMOS ? [74]
2 Gb DDR3 Hynix 40 nm
2011 ? 16 Gb DDR3 Hynix 40 nm CMOS ? [82]
2 Gb DDR4 Hynix 30 nm CMOS ? [82]
2013 ? ? LPDDR4 Samsung 20 nm CMOS ? [82]
2014 ? 8 Gb LPDDR4 Samsung 20 nm CMOS ? [83]
2015 ? 12 Gb LPDDR4 Samsung 20 nm CMOS ? [72]
2018 ? 8 Gb LPDDR5 Samsung 10 nm FinFET ? [84]
128 Gb DDR4 Samsung 10 nm FinFET ? [85]

SGRAM and HBM[]

Synchronous graphics random-access memory (SGRAM) and High Bandwidth Memory (HBM)
Date of introduction Chip name Capacity (bits) SDRAM type Manufacturer(s) Process MOSFET Area Ref
November 1994 HM5283206 8 Mibit SGRAM (SDR) Hitachi 350 nm CMOS 58 mm² [86][87]
December 1994 µPD481850 8 Mibit SGRAM (SDR) NEC ? CMOS 280 mm² [88][89]
1997 µPD4811650 16 Mibit SGRAM (SDR) NEC 350 nm CMOS 280 mm² [90][91]
September 1998 ? 16 Mibit SGRAM (GDDR) Samsung ? CMOS ? [69]
1999 KM4132G112 32 Mibit SGRAM (SDR) Samsung ? CMOS ? [92]
2002 ? 128 Mibit SGRAM (GDDR2) Samsung ? CMOS ? [93]
2003 ? 256 Mibit SGRAM (GDDR2) Samsung ? CMOS ? [93]
SGRAM (GDDR3)
March 2005 K4D553238F 256 Mibit SGRAM (GDDR) Samsung ? CMOS 77 mm² [94]
October 2005 ? 256 Mibit SGRAM (GDDR4) Samsung ? CMOS ? [95]
2005 ? 512 Mibit SGRAM (GDDR4) Hynix ? CMOS ? [74]
2007 ? 1 Gibit SGRAM (GDDR5) Hynix 60 nm
2009 ? 2 Gibit SGRAM (GDDR5) Hynix 40 nm
2010 K4W1G1646G 1 Gibit SGRAM (GDDR3) Samsung ? CMOS 100 mm² [96]
2012 ? 4 Gibit SGRAM (GDDR3) SK Hynix ? CMOS ? [82]
2013 ? ? HBM
March 2016 MT58K256M32JA 8 Gibit SGRAM (GDDR5X) Micron 20 nm CMOS 140 mm² [97]
June 2016 ? 32 Gibit HBM2 Samsung 20 nm CMOS ? [98][99]
2017 ? 64 Gibit HBM2 Samsung 20 nm CMOS ? [98]
January 2018 K4ZAF325BM 16 Gibit SGRAM (GDDR6) Samsung 10 nm FinFET ? [100][101][102]

See also[]

  • DRAM price fixing
  • Flash memory
  • List of device bit rates
  • Memory bank
  • Memory geometry

References[]

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Further reading[]

  • Brent Keeth, R. Jacob Baker, Brian Johnson, Feng Lin. (2008). DRAM Circuit Design: Fundamental and High-Speed Topics. John Wiley & Sons.
  • Bruce Jacob, Spencer W. Ng, David T. Wang (2008). Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann Publishers.

External links[]

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