Compressed instructions

In computing, compressed instructions are a compact variation of the instruction set of a microprocessor aimed at increasing the code density of executable programs. They are a solution to the usual increased application binary sizes found on RISC architectures. Typically these machines have 32-bit instruction words, whilst the 'compressed mode' will have shortened 16-bit instructions, achieved via various compromises: only accessing a subset of the registers, more use of specific registers, and 2-operand arithmetic (rather than the usual 3-operand form found in RISC).

History

In the early 1990s, engineers at Japanese company Hitachi found ways to compress RISC instruction sets so they fit in even smaller memory systems than CISC instruction sets. They developed a compressed instruction set for their SuperH series of microprocessors, introduced in 1992.

This strategy later appeared in the ARM architecture, after ARM Holdings licensed SuperH patents as a basis for its Thumb instruction set. ARM's use in mobile devices and embedded systems incentived such economies (some systems would have 16-bit external busses to reduce costs). It was later copied by other RISC vendors.

Example support

• SuperH
• ARM architecture, Thumb
• MIPS architecture, MIPS16e ASE
• PowerPC/Power ISA Variable Length Encoding (VLE)
• RISC-V has an ISA designed with a compressed mode from the outset, rather than a retrofit.
• Adapteva Epiphany

Alternatives

The Hitachi SH-4 architecture used 16-bit instructions from the outset, with a 16-entry register file and 2-operand instructions. CISC architectures such as the 68000 can have improved code density compared to RISC machines.

Code may also be compressed and decompressed by software, using arbitrary encodings.